ST72371 datasheet(43/94 Pages) STMICROELECTRONICS

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ST72371/ST72372

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = OC1E

Output Compare 1 Enable.

0: Output Compare 1 function is enabled, but the

OCMP1 pin is a general I/O.

1: Output Compare 1 function is enabled, the

OCMP1 pin is dedicated to the Output Compare

1 capability of the timer.

Bit 6 = OC2E

Output Compare 2 Enable.

0: Output Compare 2 function is enabled, but the

OCMP2 pin is a general I/O.

1: Output Compare 2 function is enabled, the

OCMP2 pin is dedicated to the Output Compare

2 capability of the timer.

Bit 5 = OPM

One Pulse Mode.

0: One Pulse Mode is not active.

1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

Bit 4 = PWM

Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depends on the value of OC2R regis-

ter.

Bit 3, 2 = CC1-CC0

Clock Control.

The value of the timer clock depends on these bits:

Table 14. Clock Control Bits

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = EXEDG

External Clock Edge.

This bit determines which type of level transition

on the external clock pin EXTCLK will trigger the

free running counter.

0: A falling edge triggers the free running counter.

1: A rising edge triggers the free running counter.

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Timer Clock

CC1

CC0

fCPU /4

fCPU /2

fCPU /8

External Clock (where

available)

ST72371 Datasheet(PDF) 43 Page - STMicroelectronics

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