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AT52SC1283J Datasheet(PDF) 47 Page - ATMEL Corporation

Part # AT52SC1283J
Description  128-Mbit Flash 32-Mbit/64-Mbit
PDF  52 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT52SC1283J Datasheet(HTML) 47 Page - ATMEL Corporation

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47
3530B–STKD–2/4/05
AT52SC1283J/1284J [Preliminary]
50.4
Page Write Cycle
(Address Controlled, ZZ = V
IH)
Notes:
1. A write occurs during the overlap (t
WP) of low PCS1 and PWE. A write begins when PCS1 goes low and PWE goes low with
asserting PUB or PLB for single byte operation or simultaneously asserting PUB and PLB for double byte operation. A write
ends at the earliest transition when PCS1 goes high and PWE goes high. The t
WP is measured from the beginning of write to
the end of write.
2. tCW is measured from the PCS1 going low to end of write.
3. t
AS is measured from the address valid to the beginning of write.
4. t
WR is measured from the end of write to the address change. tWR applied in case a write ends as PCS1 or PWE going high.
5. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 10 µs.
High-Z
Data Undefined
Data Valid
t
WHZ
High-Z
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
A4~ A20
PCS1
PUB, PLB
WE
Data In
Data Out
A0~ A3
t
OW
t
DH
t
DW
t
DH
t
DW
t
DH
t
DW
t
DH
t
DW
t
DH
t
DW
t
DH
t
DW
t
DH
t
DW
t
DH
t
DW
t
WC
t
PC
t
PC
t
PC
t
PC
t
PC
t
PC
t
PC
t
MRC
t
AS (3)



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