LTC1867LIGN datasheet(12/16 Pages) LINER

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LTC1863L/LTC1867L

1863L7Lf

compensation pin, REFCOMP, must be bypassed with a

10µF ceramic or tantalum in parallel with a 0.1µF ceramic

for best noise performance.

Digital Interface

The LTC1863L and LTC1867L have a very simple digital

interface that is enabled by the control input, CS/CONV. A

logic rising edge applied to the CS/CONV input will initiate

a conversion. After the conversion, taking CS/CONV low

will enable the serial port and the ADC will present digital

data in two’s complement format in bipolar mode or

straight binary format in unipolar mode, through the SCK/

SDO serial port.

Internal Clock

The internal clock is factory trimmed to achieve a typical

conversion time of 3.2µs and a maximum conversion

time, 3.7µs, over the full operating temperature range. The

typical acquisition time is 1.68µs, and a throughput sam-

pling rate of 175ksps is tested and guaranteed.

Automatic Nap Mode

The LTC1863L and LTC1867L go into automatic nap mode

when CS/CONV is held high after the conversion is com-

plete. With a typical operating current of 750µA and auto-

matic 170µA nap mode between conversions, the power

dissipation drops with reduced sample rate. The ADC only

keeps the VREFand REFCOMPvoltagesactivewhenthepart

is in the automatic nap mode. The slower the sample rate

allows the power dissipation to be lower (see Figure 5).

REFERENCE

AMP

10µF

2.2µF

REFCOMP

GND

VREF

1.25V

2.5V

LTC1863L/LTC1867L

1863L7L F04a

BANDGAP

REFERENCE

0.1µF

10µF

1863L7L F04b

LT1790A-1.25

VOUT

VIN

VREF

LTC1863L/

LTC1867L

GND

REFCOMP

2.2µF

band between DC and half the sampling frequency. THD is

expressed as:

THD

VVV

log

...

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through VN are the amplitudes of the

second through Nth harmonics.

Internal Reference

The LTC1863L and LTC1867L have an on-chip, tempera-

ture compensated, curvature corrected, bandgap refer-

ence that is factory trimmed to 1.25V. It is internally

connected to a reference amplifier and is available at VREF

(Pin 10). A 3k resistor is in series with the output so that

it can be easily overdriven by an external reference if

better drift and/or accuracy are required as shown in

Figure 4. The reference amplifier gains the VREF voltage by

2x to 2.5V at REFCOMP (Pin 9). This reference amplifier

Figure 4b. Using the LT1790A-1.25 as an External Reference

Figure 4a. LT1867L Reference Circuit

APPLICATIO S I FOR ATIO

Figure 5. Supply Current vs fSAMPLE

fSAMPLE (ksps)

500

600

700

800

100

1000

1863L7L G09

400

300

200

100

VDD = 2.7V

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