CDK1301 datasheet(5/12 Pages) CADEKA

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Data Sheet

Electrical Characteristics

(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,

ƒIN = 70MHz, dual channel mode; unless otherwise noted)

symbol

parameter

conditions

Min

typ

Max

units

Power Supply Requirements

AVcc

Analog Voltage Supply(2)

4.75

5.0

5.25

OVDD

Digital Voltage Supply(2)

2.75

5.25

AIcc

Current(1)

110

Current Power-down(1)

+25°C

4.8

5.5

OIDD

Current

OVDD = 3.0V, 10pF load

Single Mode

Parallel Mode

Interleave Mode

Power Dissipation(1)

425

550

Common Mode Reference Output

Voltage(1)

2.44

2.5

2.56

Voltage Tempcp

ppm/°C

Open Impedance

IOUT = ±50µA

1.07

kΩ

PSRR

Power Supply Rejection Ratio

47.5

mV/V

Clock and Reset Inputs (Differential and Single-Ended)

VDIFF

Differental Signal Amplitude(2)

400

mVpp

VIHD

Differental High Input Voltage(2)

1.4

AVcc

VILD

Differental Low Input Voltage(2)

3.9

VCMD

Differental Common Mode Input(2)

1.2

4.1

VIH

Single-Ended High Input Voltage(1)

1.8

VIL

Single-Ended Low Input Voltage(2)

1.2

IIH

High Input Current(1)

VID = 1.5V

-100

+100

µA

IIL

Low Input Current(1)

VID = 1.5V

-100

+100

µA

Power Down and Mode Control Inputs (Single-Ended)

High Input Voltage(2)

2.0

AVcc

Low Input Voltage(2)

1.0

Max Input Current Low(1)

-100

0.5

+100

µA

Max Input Current High <4.0V(1)

-100

+100

µA

Digital Outputs

Logic “1“ Voltage(1)

IOH = -0.5mA

OVDD-2.0

Logic “0“ Voltage(1)

IOL = +1.6mA

0.2

TR/TF Data

OVDD = 3V, 10pF load

3.3/3.0

OVDD = 5V, 10pF load

2.3/1.9

TR/TF DCLK

OVDD = 3V, 10pF load

1.2/1.0

OVDD = 5V, 10pF load

0.7/0.6

notes:

1. 100% production tested at +25°C.

2. Parameter is guaranteed (but not tested) by design and characterization data.

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