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TMS320VC5421 Datasheet(PDF) 63 Page - Texas Instruments |
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TMS320VC5421 Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 88 page  TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 – DECEMBER 1999 63 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 externally generated wait states timing timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 30 and Figure 31) MIN MAX UNIT tsu(RDY) Setup time, READY before CLKOUT low 5 ns th(RDY) Hold time, READY after CLKOUT low 0 ns tv(RDY)IOSTRB Valid time, READY after IOSTRB low‡ 5H–8 ns th(RDY)IOSTRB Hold time, READY after IOSTRB low‡ 5H ns † The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using READY, at least two software wait states must be programmed. ‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT. tsu(RDY) IOSTRB READY PPA[18:0] CLKOUT th(RDY) Wait State Generated by READY Wait States Generated Internally tv(RDY)IOSTRB th(RDY)IOSTRB Figure 30. I/O Port Read With Externally Generated Wait States |
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