TMS370CX32 datasheet(15/43 Pages) TI

15 / 43 page

TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C – FEBRUARY 1990 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

privileged operation and EEPROM write protection override (continued)

Table 8. Privilege Bits

CONTROL BIT

NAME

LOCATION

CONTROL BIT

SCCRO

P010.5

P010.6

PF AUTO WAIT

OSC POWER

SCCR1

P011.2

P011.4

MEMORY DISABLE

AUTOWAIT DISABLE

SCCR2

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN / IDLE

HALT / STANDBY

PACTSCR

P040.0

P040.1

P040.2

P040.3

P040.4

PACT PRESCALE SELECT 0

PACT PRESCALE SELECT 1

PACT PRESCALE SELECT 2

PACT PRESCALE SELECT 3

FAST MODE SELECT

PACTPRI

P04F.0

P04F.1

P04F.2

P04F.3

P04F.4

P04F.5

P04F.7

PACT WD PRESCALE SELECT 0

PACT WD PRESCALE SELECT 1

PACT MODE SELECT

PACT GROUP 3 PRIORITY

PACT GROUP 2 PRIORITY

PACT GROUP 1 PRIORITY

PACT STEST

ADPRI

P07F.5

P07F.6

P07F.7

AD ESPEN

AD PRIORITY

AD STEST

† The privilege bits are shown in a bold typeface in the peripheral file

frame 1 section.

low-power and IDLE modes

The TMS370Cx32 devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the

time when the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the IDLE instruction when the PWRDWN / IDLE bit in SCCR2 has been set to 1. The

HALT / STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity is stopped;

however, the oscillator, internal clocks, the PACT counter, and the first PACT command entry remain active in

all modules. System processing is suspended until a qualified interrupt (hardware RESET or external interrupt

on INT1, INT2, or INT3) is detected.

In the HALT mode (HALT / STANDBY = 1), the TMS370Cx32 is placed in its lowest power consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is

suspended until a qualified interrupt (hardware RESET or external interrupt on the INT1, INT2, or INT3) is

detected. The power-down mode-selection bits are summarized in Table 9.

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