TSB41BA3DIPFP datasheet(39/59 Pages) TI

39 / 59 page

(g)

(e)/(f)

(d)

(c)

(b)

(a)

d0, d1, . . .

Link Controls CTL and D

PHY High-Impedance CTL and D Outputs

D0–D7

CTL0, CTL1

SYSCLK

00/01

00/SP

TSB41BA3D

www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009

When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first

bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have

been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle and then asserts

idle for one additional cycle before releasing the interface bus and putting the CTL and D terminals in a

high-impedance state. The PHY then regains control of the interface bus.

The hold state asserted at the end-of-packet transmission indicates to the PHY that the LLC requests to send

another packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation

request by waiting the required minimum packet separation time and then asserting grant as before. This

function can be used to send a unified response after sending an acknowledge or to send consecutive

isochronous packets during a single isochronous period. Unless multispeed concatenation is enabled, all packets

transmitted during a single bus ownership must be of the same speed (because the speed of the packet is set

before the first packet). If multispeed concatenation is enabled (when the EMSC bit of PHY register 5 is set),

then the LLC must specify the speed code of the next concatenated packet on the D terminals when it asserts

hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the speed

code that precedes received packet data as given in Table 23.

After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the

CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling

idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC,

an extra clock period is allowed so that both sides of the interface can operate on registered versions of the

interface signals.

SPD = Speed code, see Table 23. d0–dn = Packet data

Figure 17. Normal Packet Transmission Timing

The sequence of events for a normal packet transmission is as follows:

a. Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over control of

the interface to the link so that the link can transmit a packet. The PHY releases control of the interface (that

is, it places its CTL and D outputs in a high-impedance state) following the idle cycle.

b. Optional idle cycle. The link can assert at most one idle cycle preceding assertion of either hold or transmit.

This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.

c. Optional hold cycles. The link can assert hold for up to 47 cycles preceding assertion of transmit. These hold

cycle(s) are optional; the link is not required to assert hold preceding transmit.

d. Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with the

data on the D lines.

e. Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on the

CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in order to

transmit a concatenated packet. The link asserts idle to indicate that packet transmission is complete and the

PHY can release the serial bus. The link then asserts idle for one more cycle following this hold or idle cycle

before releasing the interface and returning control to the PHY.

Concatenated packet speed code. If multispeed concatenation is enabled in the PHY, then the link asserts a

speed code on the D lines when it asserts hold to terminate packet transmission. This speed code indicates

the transmission speed for the concatenated packet that is to follow. The encoding for this concatenated

Submit Documentation Feedback

Product Folder Link(s): TSB41BA3D

TSB41BA3DIPFP Datasheet(PDF) 39 Page - Texas Instruments

TSB41BA3DIPFP Datasheet(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL