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CY22801
Document #: 001-15571 Rev. *B
Page 5 of 7
Test Circuit
Figure 3. Test Circuit Diagram
Timing Definitions
Figure 4. Duty Cycle Definition; DC = t2/t1
Figure 5. Rise and Fall Time Definitions
Notes
5. Skew value guaranteed when outputs are generated from the same divider bank.
6. Jitter measurement may vary. Actual jitter is dependent on input jitter and edge rate, number of active outputs, input and output frequencies, supply voltage, temperature,
and output load. For more information, refer to the application note, Jitter in PLL-based Systems: Causes, Effects, and Solutions.
AC Electrical Characteristics[2]
Parameter
Name
Description
Min
Typ
Max
Unit
fREFC
Reference Frequency -
crystal
8–
30
MHz
fREFD
Reference Frequency - driven
1
–
133
MHz
fOUT
Output Frequency,
Commercial Grade
1–
200
MHz
Output Frequency, Industrial
Grade
1
–
166.6
MHz
DC
Output Duty Cycle
Duty Cycle is defined in Figure 4, 50% of
VDD
45
50
55
%
t3
Output Rising Edge Slew
Rate
20% - 80% of VDD
0.8
1.4
–
V/ns
t4
Output Falling Edge Slew
Rate
80% - 20% of VDD
0.8
1.4
–
V/ns
t5
[5]
Skew
Output-output skew between related
outputs
––
250
ps
t6
[6]
Clock Jitter
Peak-to-peak period jitter
–
250
–
ps
t10
PLL Lock Time
–
–
3
ms
0.1
μF
VDD
CLKout
CLOAD
GND
OUTPUTS
t1
t2
CLK
50%
50%
t3
CLK
80%
20%
t4
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