4

October 2002

SPT7750

GENERAL DESCRIPTION

The SPT7750 is one of the fastest monolithic 8-bit parallel

flash A/D converters available today. The nominal conver-

sion rate is 500 MSPS and the analog bandwidth is in

excess of 900 MHz. A major advance over previous flash

converters is the inclusion of 256 input preamplifiers

between the reference ladder and input comparators (see

block diagram). This not only reduces clock transient kick-

back to the input and reference ladder due to a low AC

beta, but also reduces the effect of the dynamic state of

the input signal on the latching characteristics of the input

comparators. The preamplifiers act as buffers and stabi-

lize the input capacitance so that it remains constant over

different input voltage and frequency ranges and therefore

makes the part easier to drive than previous flash convert-

ers. The preamplifiers also add a gain of two to the input

signal so that each comparator has a wider overdrive or

threshold range to “trip” into or out of the active state. This

gain reduces metastable states that can cause errors at

the output.

The SPT7750 has true differential analog and digital data

paths from the preamplifiers to the output buffers (Current

Mode Logic) for reducing potential missing codes while

rejecting common mode noise.

Signature errors are also reduced by careful layout of the

analog circuitry. The output drive capability of the device

can provide full ECL swings into 50 Ω loads.

Figure 1 – SPT7750 Typical Interface Circuit

50 W

*

U1

+

–

22 W

*

U1

–

22 W

–5.2 V

2N2907

50 W

–2.0 V

Reference

Convert

U2

50 W

–2 V

Pulldown

(Analog)

CLK

CLK

–5.2 V

D8B (OVR)

D7B (MSB)

D6B

D5B

D4B

D3B

D2B

D1B

D0B (LSB)

D8A (OVR)

D7A (MSB)

D6A

D5A

D4A

D3A

D2A

D1A

D0A (LSB)

–2.0 V

Pulldown

(Digital)

.1 µF

FB = Ferrite bead

U1 = OP291 or equivalent with low offset/noise.

R= 1 kW; 0.1% matched.

= AGND

= DGND

U2 = ON Semiconductor ECLinPS LITE, MC10EL16,

differential receiver with 250 ps (typ) propagation delay.

U3 = MC10EL16 or MC100EL16.

* = 10 µF Tantalum Capacitor and 0.1 µF Chip Capacitor

** = Care must be taken to avoid exceeding the maximum rating

for the input, especially during power up sequencing of the

analog input driver.

R

R

*

–5.2 V

FB

DRB

DRB

DRA

DRA

U3

U3

DRA (DATA READY)

DRA (DATA READY)

DRB (DATA READY)

DRB (DATA READY)

–2.0 V Pulldown (Digital)