High Voltage Step Down Regulator

A4447

8

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

R1

R2

D1

RTSET

COUT

CIN1

CIN2

L1

U1

VIN

VOUT

CBOOT

CBYP

GND

GND

GND

GND

Recommended PCB Layout

The large star ground area on the populated side of the PCB, shown in the diagram as the GND nodes, supports high current throughput, and allows

the VOUT node to be located as close as practical to the A4447 (U1). Thermal conduction from the A4447 is enhanced by direct contact of its

exposed thermal pad to the smaller ground area under the A4447. This area is connected by thermal vias to the large copper ground plane on the

unpopulated side of the PCB.

Star Ground

Exposed copper thermal

ground area on the

unpopulated side of the PCB

In order to minimize the effects of ground bounce and offset

issues, it is important to have a low impedance ground located

very close to the device. This grounding scheme is known as star

grounding. It is likely that a ground plane will be necessary to

meet thermal requirements. The recommended land pattern illus-

trates how to create a low impedance ground that will also assist

with removing thermal energy from the device.

The input capacitor must be placed as close as possible to the

VIN terminal because during the on cycle it is responsible for

supplying the current to the switcher. During the off cycle, the

current path is from the negative terminal of the COUT cap,

through the diode and inductor, and then to the load. As a result,

COUT and the rectifier diode must share the connection at the

negative terminal of the CIN capacitor in order to reduce ground

bounce when the diode is conducting.

The inductor should be connected as close as possible to the

switching node to minimize noise. Some applications may require

a shielded inductor due to EMI restrictions. This will depend on

the application and parameters defined by the system that will

host the regulator.

off-times are used, the resistance on the RTSET pin can be quite

large. When designing the layout, try to keep RTSET away from

the inductor and switching node. It is also beneficial to keep the

trace as short as possible to reduce the effect of noise injection.

Because of this layout guideline, the TSET pin is located on the

other side of the device, away from the switching node.

The FB resistor network should have a lower impedance to avoid

interference from the switching node. Because the impedance

on the FB node can be controlled, it is not as critical to keep the

network isolated. It is important to keep the ground trace short so

that ground bounce cannot effect the output voltage regulation.

R2

R1

L1

COUT

CIN1

CIN2

CBYP

D1

RTSET

CBOOT

1

A4447

ENB

LX

VBIAS

VIN

GND

FB

TSET

BOOT

PAD