MPC89X53AF datasheet(22/38 Pages) MEGAWIN

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IP (or XICON) and IPH are combined to form 4-level priority interrupt as the following table.

Priority

{IPH.x , IP.x}

Level

1 (highest)

SFR: XICON (External Interrupt Control):

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2

PX3 : If set, Set priority for external interrupt 3 higher

EX3 : If set, Enables external interrupt 3.

IE3

: Interrupt 3 Edge flag. Sets by hardware when external interrupt edge detected. Cleared when

interrupt processed.

IT3

: Interrupt 3 type control bit. Set/Cleared by software to specified falling edge/low level triggered

interrupt.

PX2 : If set, Set priority for external interrupt 3 higher

EX2 : If set, enables external interrupt 2.

IE2

: Interrupt 2 Edge flag. Sets by hardware when external interrupt edge detected. Cleared when

interrupt processed.

IT2

: Interrupt 2 types control bit. Set/Cleared by software to specify falling edge/low level triggered

interrupt.

Watchdog Timer

8-bit pre-scalar timer

15-bit WDT

PS0

PS1

PS2

RESET

ENW

CLK/12

CLRW

IDLE

WIDL

MPC89x53A Data Sheet

MEGAWIN

MPC89x53AF Datasheet(PDF) 22 Page - Megawin Technology Co., Ltd

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