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25LC080C Datasheet(PDF) 8 Page - Microchip Technology |
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25LC080C Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 24 page  25LCXXX DS22131C-page 8 Preliminary © 2009 Microchip Technology Inc. 3.0 FUNCTIONAL DESCRIPTION 3.1 Principles of Operation The 25LCXXX are Mid-Density Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular micro- controller families, including Microchip’s PIC® micro- controllers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/ O lines programmed properly in firmware to match the SPI protocol. The 25LCXXX contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25LCXXX in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. Block Diagram SI SO SCK CS HOLD WP STATUS Register I/O Control Memory Control Logic X Dec HV Generator EEPROM Array Page Latches Y Decoder Sense Amp. R/W Control Logic VCC VSS TABLE 3-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register |
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