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20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373

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11

11 - 12

General Description

Features

Functional Diagram

Typical Applications

7 GHz INTEGER N SYNTHESIZER

(N = 12 - 259)

v03.0709

The HMC698LP5(E) is a frequency synthesizer with

a wideband reversible polarity digital PFD and lock

detect output. The divider operates unconditionally

from 80 - 7000 MHz with a continuous integer division

ratio of 12 to 259. The HMC698LP5(E) high frequency

operation along with ultra low phase noise floor make

possible synthesizers with wide loop bandwidth and

low N resulting in fast settling and very low phase

noise. When used in conjunction with a differential

loop filter, the HMC698LP5(E) can be used to phase

lock a VCO to a reference oscillator.

Ultra Low SSB Phase Noise Floor:

-153 dBc/Hz @ 10 kHz offset @ 100 MHz

Reference Frequency.

Programmable Divider (N= 12 - 259) Operating

up to 7 GHz

Open Collector Output Buffer Amplifiers for

Interfacing w/ Op-Amp Based Loop Filter

Reversible Polarity PFD w/ Lock Detect Output

The HMC698LP5(E) is ideal for:

• Satellite Communication Systems

• Point-to-Point Radios

• Military Applications

• Sonet Clock Generation

Parameter

Conditions

Min.

Typ.

Max.

Units

Maximum Ref. Input Frequency

1300

MHz

Minimum Ref. Input Frequency

10

MHz

Reference Input Power Range

100 MHz Frequency

-5

+5

dBm

Maximum VCO Input Frequency

7000

MHz

Minimum VCO Input Frequency

80

MHz

VCO Input Power Range

100 MHz Input Frequency

-10

+5

dBm

PFD Output Voltage

2000

mV, Pk - Pk

PFD Gain

Gain = Vpp / 2π Rad.

0.32

V/Rad.

SSB Phase Noise

@ 10 kHz Offset @ 100 MHz Square Wave Ref. Input

Pin= 0 dBm

-153

dBc/Hz

Total Supply Current

310

mA

[1] Maximum frequencies may be limited by available counter division ratio.

[2] Square wave input achieves best phase noise at lower ref. frequency (see sine & square wave comparison plots)