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CPC7583MATR Datasheet(PDF) 15 Page - Clare, Inc. |
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CPC7583MATR Datasheet(HTML) 15 Page - Clare, Inc. |
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15 / 21 page ![]() CPC7583 R06 www.clare.com 15 20 Hz ringing hold this input state for 25 ms. During this hold period, toggle the inputs from the ringing state to the talk state. After the 25 ms, release TSD to return switch control to the input pins INTESTout, INRINGING, INTESTin and the latch control pin. 2.2.1 Make-Before-Break Operation (Ringing to Talk Transition) 2.2.2 Break-Before-Make Operation (Ringing to Talk Transition) 2.3 Alternate Break-Before-Make Operation Note that break-before-make operation can also be achieved using TSD as an input. In lines 2 and 3 of the table “Break-Before-Make Operation (Ringing to Talk Transition)” on page 15, instead of using the logic input pins to force the all-off state, force TSD to ground. This overrides the logic inputs and also forces the all off state. Hold this state for one-half of the ringing cycle. During this TSD forced all-off state, change the inputs from the power ringing state (INRING = 1, INTESTIN = 0, INTESTOUT = 0) to the talk state (INRING = 0, INTESTIN = 0, INTESTOUT = 0). After the hold period, release TSD to return switch control to the input pins which will set the talk state. 2.4 Data Latch The CPC7583 has an integrated data latch. The latch operation is controlled by logic-level input at the LATCH pin. The data input of the latch are the input pins, while the output of the data latch is an internal node used for state control. When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected by a change in switch state. When the LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from State INRINGING INTESTIN INTESTOUT Latch TSD Timing Break Switches 1 and 2 Ring Return Switch 3 Ring Access Switch 4 All Other Test Switches Ringing 1 0 0 0 Floating - Off On On Off Make- before- break 0 0 0 Floating SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of ringing. In this transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. On Off On Off Talk 0 0 0 Floating Zero-cross current has occurred On Off Off Off State INRINGING INTESTIN INTESTOUT Latch TSD Timing Break Switches 1 and 2 Ring Return Switch 3 Ring Access Switch 4 All Other Test Switches Ringing 1 0 0 0 Floating - Off On On Off All off 1 0 1 Floating Hold this state for one-half of ringing cycle. SW4 waiting for zero current to turn off. Off Off On Off All off 1 0 1 Floating Zero current has occurred. SW4 has opened Off Off Off Off Talk 0 0 0 Floating Close break switches On Off Off Off |
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