ATmega16 datasheet(52/357 Pages) ATMEL

52 / 357 page

2466S–AVR–05/09

ATmega16(L)

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 20 summarizes the control signals for the pin value.

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 23, the PINxn Register bit and the preceding latch consti-

tute a synchronizer. This is needed to avoid metastability if the physical pin changes value near

the edge of the internal clock, but it also introduces a delay. Figure 24 shows a timing diagram of

the synchronization when reading an externally applied pin value. The maximum and minimum

propagation delays are denoted t

pd,max and tpd,min respectively.

Figure 24. Synchronization when Reading an Externally Applied Pin Value

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As

indicated by the two arrows t

pd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

Table 20. Port Pin Configurations

DDxn

PORTxn

PUD

(in SFIOR)

I/O

Pull-up

Comment

Input

Tri-state (Hi-Z)

Input

Yes

Pxn will source current if ext. pulled

low.

Input

Tri-state (Hi-Z)

Output

Output Low (Sink)

Output

Output High (Source)

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

r17

in r17, PINx

0xFF

0x00

tpd, max

XXX

tpd, min

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