| Electronic Components Datasheet Search |
|
MPC5121E Datasheet(PDF) 65 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC5121E Datasheet(HTML) 65 Page - Freescale Semiconductor, Inc |
|
65 / 86 page ![]() Electrical and Thermal Characteristics MPC5121E/MPC5123 Data Sheet, Rev. 4 Freescale Semiconductor 65 NOTE Output timing is specified at a nominal 50 pF load. Figure 45. Timing Diagram – I2C Input/Output 3.3.19 J1850 See the MPC5121e/MPC5123 Reference Manual. 3.3.20 PSC The Programmable Serial Controllers (PSC) support different modes of operation (UART, Codec, AC97, SPI). UART is an asynchronous interface, there is no AC characteristic. 3.3.20.1 Codec Mode (8,16,24 and 32-bit)/I2S Mode NOTE Output timing is specified at a nominal 50 pF load. Table 41. Timing Specifications – 8,16, 24, and 32-bit CODEC/I2S Master Mode Sym Description Min Typ Max Units SpecID 1 Bit Clock cycle time, programmed in CCS register 40.0 — — ns A20.1 2 Clock duty cycle 45 50 55 %1 1 Bit Clock cycle time A20.2 3 Bit Clock fall time — — 7.9 ns A20.3 4 Bit Clock rise time — — 7.9 ns A20.4 5 FrameSync valid after clock edge — — 8.4 ns A20.5 6 FrameSync invalid after clock edge — — 8.4 ns A20.6 7 Output Data valid after clock edge — — 9.3 ns A20.7 8 Input Data setup time 6.0 — — ns A20.8 1 2 3 4 5 6 7 8 9 SCL SDA |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |