HT68F20 datasheet(86/210 Pages) HOLTEK

86 / 210 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Rev.1.00

November 3, 2009

Bit 3

T0OC: TP0_0, TP0_1 Output control bit

Compare Match Output Mode

0: Initial low

1: Initial high

PWM Mode

0: Active low

1: Active high

This is the output control bit for the TM output pin. Its operation depends upon whether TM is

being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is

in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of

the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM

signal is active high or active low.

Bit 2

T0POL: TP0_0, TP0_1 Output polarity Control

0: Non-invert

1: Invert

This bit controls the polarity of the TP0_0 or TP0_1 output pin. When the bit is set high the TM

output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the

Timer/Counter Mode.

Bit 1

T0DPX: TM0 PWM period/duty Control

0: CCRP - period; CCRA - duty

1: CCRP - duty; CCRA - period

This bit, determines which of the CCRA and CCRP registers are used for period and duty

control of the PWM waveform.

Bit 0

T0CCLR: Select TM0 Counter clear condition

0: TM0 Comparatror P match

1: TM0 Comparatror A match

This bit is used to select the method which clears the counter. Remember that the Compact TM

contains two comparators, Comparator A and Comparator P, either of which can be selected to

clear the internal counter. With the T0CCLR bit set high, the counter will be cleared when a

compare match occurs from the Comparator A. When the bit is low, the counter will be cleared

when a compare match occurs from the Comparator P or with a counter overflow. A counter

overflow clearing method can only be implemented if the CCRP bits are all cleared to zero.

The T0CCLR bit is not used in the PWM Mode.

HT68F20 Datasheet(PDF) 86 Page - Holtek Semiconductor Inc