ADP151AUJZ-2.8-R7 datasheet(14/24 Pages) AD

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ADP151

Rev. 0 | Page 14 of 24

Figure 32 through Figure 36 show the typical performance of the

4 V LDO circuit.

The noise performance of the 4 V LDO circuit is only about 1 μV

worse than the same LDO used at 3.3 V because the output noise of

the circuit is almost solely determined by the LDO and not the

external components. The small difference may be attributed to the

internally generated noise in the LDO ground current working

with R2. By keeping R2 small, this noise contribution can be

minimized.

The PSRR of the 4 V circuit is as much as 10 dB poorer than the

3.3. V LDO with 500 mV of headroom because the ground current

of the LDO varies somewhat with input voltage. This, in turn,

modulates VOFFSET and reduces the PSRR of the regulator. By

increasing the headroom to 1 V, the PSRR performance is nearly

restored to the performance of the fixed output LDO.

4.04

4.03

4.02

4.01

4.00

3.99

3.98

3.97

3.96

–40

–5

125

JUNCTION TEMPERATURE (°C)

LOAD = 10mA

LOAD = 20mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

Figure 32. 4 V LDO Circuit, Typical Load Regulation over Temperature

VIN (V)

LOAD = 10mA

LOAD = 20mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

4.040

4.035

4.030

4.025

4.020

4.015

4.010

4.005

4.000

4.4

5.2

5.4

4.8

4.6

5.0

Figure 33. 4 V LDO Circuit, Typical Line Regulation over Load Current

100

LOAD CURRENT (mA)

Figure 34. 4 V Load Circuit, Typical RMS Output Noise, 10 Hz to 100 kHz

CH1 100mA

CH2 50mV

M40µs

A CH1

52.0mA

T 10.20%

Figure 35. 4 V Load Circuit, Typical PSRR vs. Load Current, 1 V Headroom

CH1 100mA

CH2 50mV

M40µs

A CH1

52.0mA

T 10.20%

Figure 36. 4 V Load Circuit, Typical PSRR vs. Load Current, 500 mV Headroom

ADP151AUJZ-2.8-R7 Datasheet(PDF) 14 Page - Analog Devices

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