PCA9502_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 13 October 2006

5 of 25

NXP Semiconductors

PCA9502

7.2 Interrupts

The PCA9502 has interrupt generation capability. The interrupt enable register (IOIntEna)

enables interrupts due to I/O pin change of state, and the IRQ signal in response to an

interrupt generation.

8.

Register descriptions

The programming combinations for register selection are shown in Table 5.

[1]

Other addresses 0x00 through 0x09, 0x0F are reserved and should not be accessed (read or write).

[2]

These bits are reserved and should be set to 0.

8.1 Programmable I/O pins Direction register (IODir)

This register is used to program the I/O pins direction. Bit 0 to bit 7 control GPIO0 to

GPIO7.

Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending

interrupt will be cleared, that is, the interrupt signal will be negated.

Table 5.

Register map - read/write properties

Register name

Read mode

Write mode

IODir

I/O pin direction

I/O pin direction

IOState

I/O pin states

n/a

IOIntEna

I/O interrupt enable register

I/O interrupt enable register

IOControl

I/O pins control

I/O pins control

Table 6.

PCA9502 internal registers

Register

address

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

General Register Set

0x0A[1]

IODir

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x0B[1]

IOState

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x0C[1]

IOIntEna

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

0x0D[1]

reserved

[2]

reserved

[2]

reserved

[2]

reserved

[2]

reserved

[2]

reserved

[2]

reserved

[2]

reserved

[2]

reserved

[2]

0x0E[1]

IOControl

reserved

[2]

reserved

[2]

reserved

[2]

reserved

[2]

SReset

reserved

[2]

reserved

[2]

IOLatch

R/W

Table 7.

IODir register (address 0x0A) bit description

Bit

Symbol

Description

7:0

IODir

set GPIO pins 7:0 to input or output

0 = input

1 = output