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11LC010-IP Datasheet(PDF) 13 Page - Microchip Technology |
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11LC010-IP Datasheet(HTML) 13 Page - Microchip Technology |
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13 / 44 page  2010 Microchip Technology Inc. Preliminary DS22067H-page 13 11AAXXX/11LCXXX 4.4 Write Enable (WREN) and Write Disable (WRDI) Instructions The 11XX contains a write enable latch. See Table 6-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be com- pleted internally. The WREN instruction will set the latch, and the WRDI instruction will reset the latch. The following is a list of conditions under which the write enable latch will be reset: • Power-up • WRDI instruction successfully executed • WRSR instruction successfully executed • WRITE instruction successfully executed • ERAL instruction successfully executed • SETAL instruction successfully executed FIGURE 4-4: WRITE ENABLE COMMAND SEQUENCE FIGURE 4-5: WRITE DISABLE COMMAND SEQUENCE Note: The WREN and WRDI instructions must be terminated with a NoMAK following the command byte. If a NoMAK is not received at this point, the command will be considered invalid, and the device will go into Idle mode without responding with a SAK or executing the command. 11 0 1 0 1 00 Start Header SCIO Device Address 00(1) 0 0 1 0 10 Command 10 0 1 0 0 11 Standby Pulse SCIO Note 1: For the 11XXXX1, this bit must be a ‘1’. 11 0 1 0 1 00 Start Header SCIO Device Address 00(1) 0 0 1 0 10 Command 01 0 1 0 0 10 Standby Pulse SCIO Note 1: For the 11XXXX1, this bit must be a ‘1’. |
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