LTC4280CUFD datasheet(21/28 Pages) LINER

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LTC4280

4280f

APPLICATIONS INFORMATION

remains LOW during this pulse to acknowledge receipt

of the data. If the slave fails to acknowledge by leaving

SDA high, then the master may abort the transmission by

generating a STOP condition. When the master is receiving

data from the slave, the master pulls down the SDA line

during the clock pulse to indicate receipt of the data. After

the last byte has been received the master leaves the SDA

line HIGH (not acknowledge) and issues a stop condition

to terminate the transmission.

Write Protocol

The master begins communication with a START condition

followed by the seven bit slave address and the R/W bit

set to zero, as shown in Figure 7. The addressed LTC4280

acknowledges this and then the master sends a command

byte which indicates which internal register the master

wishes to write. The LTC4280 acknowledges this and

then latches the lower three bits of the command byte

into its internal Register Address pointer. The master then

delivers the data byte and the LTC4280 acknowledges

once more and latches the data into its control register.

The transmission is ended when the master sends a STOP

condition. If the master continues sending a second data

byte, as in a Write Word command, the second data byte

is acknowledged by the LTC4280 but ignored, as shown

in Figure 8.

Read Protocol

The master begins a read operation with a START condition

followed by the seven bit slave address and the R/W bit

set to zero, as shown in Figure 9. The addressed LTC4280

acknowledges this and then the master sends a command

byte which indicates which internal register the master

wishes to read. The LTC4280 acknowledges this and then

latches the lower three bits of the command byte into its

internal Register Address pointer. The master then sends

a repeated START condition followed by the same seven

bit address with the R/W bit now set to one. The LTC4280

acknowledges and send the contents of the requested

sends a STOP condition. If the master acknowledges

the transmitted data byte, as in a Read Word command,

Figure 10, the LTC4280 repeats the requested register as

the second data byte.

Alert Response Protocol

When any of the fault bits in FAULT register D are set, an

optional bus alert is generated if the appropriate bit in

the ALERT register B is also set. If an alert is enabled, the

corresponding fault causes the ALERT pin to pull low. After

the bus master controller broadcasts the Alert Response

Address, the LTC4280 responds with its address on the

SDA line and then release ALERT as shown in Figure 11.

The ALERT line is also released if the device is addressed

by the bus master. The ALERT signal is not pulled low

again until the FAULT register indicates a different fault

has occurred or the original fault is cleared and it occurs

again. Note that this means repeated or continuing faults

do not generate alerts until the associated FAULT register

bit has been cleared.

LTC4280CUFD Datasheet(PDF) 21 Page - Linear Technology

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