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ADT7483AARQZ-R7 Datasheet(PDF) 4 Page - ON Semiconductor |
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ADT7483AARQZ-R7 Datasheet(HTML) 4 Page - ON Semiconductor |
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4 / 24 page  ADT7483A Rev. 1 | Page 4 of 24 | www.onsemi.com SMBUS TIMING SPECIFICATIONS Table 2. Parameter1 Limit at TMIN, TMAX Unit Description fSCLK 400 kHz max tLOW 4.7 μs min Clock low period, between 10% points tHIGH 4 μs min Clock high period, between 90% points tR 1 μs max Clock/data rise time tF 300 ns max Clock/data fall time tSU; STA 4.7 μs min Start condition setup time tHD; STA2 4 μs min Start condition hold time tSU; DAT3 250 ns min Data setup time tSU; STO4 4 μs min Stop condition setup time tBUF 4.7 μs min Bus free time between stop and start conditions 1 Guaranteed by design, but not production tested. 2 Time from 10% of SDATA to 90% of SCLK. 3 Time for 10% or 90% of SDATA to 10% of SCLK. 4 Time for 90% of SCLK to 10% of SDATA. SCLK SDATA tR tF tLOW tHD;DAT tHD;STA tHIGH tSU;DAT STOP START STOP START tSU;STA tSU;STO tHD;STA tBUF Figure 2. Serial Bus Timing |
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