Considerations in Use of XSTP Bit

Ensure error-free oscillation halt sensing by preventing the following:

2) Condensation on the crystal oscillator

3) Generation of noise on the PCB in the crystal oscillator

4) Application of voltage exceeding prescribed maximum ratings to the indi-

vidual pins of the IC

RS5C313

18

Oscillation Halt can be sensed by setting the XSTP (oscillator halt sensing) bit to 0 (after writing data to the control

register) and then monitoring the XSTP bit. Upon oscillator halt sensing, the XSTP bit is switched from 0 to 1. This

function can be applied to judge clock data validity.

5. Oscillator Halt Sensing

Writing of data to

control register

(in the presence of oscillation)

Power-on

from 0V

*

1

Oscillation restart

*

2

Oscillation halt

XSTP

cause operational failure. When the CE pin is held at the high level oscillation halt is not sensed and the value of the XSTP bit when the CE pin is

held at the low level is retained.

6. Typical Power Supply Circuit

OSCIN

OSCOUT

VDD

VSS

R S 5 C 3 1 3

B

A

System supply voltage

INTR

1) Connect the capacitance of the oscillation circuit to the VSS pin.

2) Mount the high- and low-frequency by-pass capacitors in parallel

and very close to the RS5C313.

3) Connect the pull-up resistor of the INTR pin to two different posi-

tions depending on whether the resistor is in use during battery

back-up.

• When not in use during battery back-up

- - - - - Position A in the left figure

• When in use during battery back-up

- - - - - Position B in the left figure

4) Timing of power supply on / off and CE terminal refer to lower part

plan.

C

0V

CE

D

MIN. 0µs

MIN. 0µs

MIN. 0µs

C,D,E : The lower limit voltage for CPU operation

Battery voltage

System supply

voltage

E