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ATA6663-FAQW Datasheet(PDF) 13 Page - ATMEL Corporation |
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ATA6663-FAQW Datasheet(HTML) 13 Page - ATMEL Corporation |
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13 / 20 page ![]() 13 9146D–AUTO–09/10 Atmel ATA6663/ATA6664 7.12 Leakage current at loss of battery; node has to substain the current that can flow under this condition; bus must remain operational under this condition VBAT disconnected V SUP_Device = GND 0V < VBUS < 18V 6I BUS_NO_Bat 0.1 2 µA A 7.13 Capacitance on pin LIN to GND 6 C LIN 20 pF D 8 LIN Bus Receiver 8.1 Center of receiver threshold V BUS_CNT = (V th_dom + Vth_rec)/2 6VBUS_CNT 0.475 × V S 0.5 × V S 0.525 × V S VA 8.2 Receiver dominant state V EN = 5V 6 V BUSdom –27 0.4 × VS VA 8.3 Receiver recessive state V EN = 5V 6 V BUSrec 0.6 × V S 40 V A 8.4 Receiver input hysteresis VHYS = Vth_rec – Vth_dom 6VBUShys 0.028 × V S 0.1 × V S 0.175 × V S VA 8.5 Pre-wake detection LIN High-level input voltage 6V LINH V S – 2V V S + 0.3V VA 8.6 Pre-wake detection LIN Low-level input voltage Switches the LIN receiver on 6 V LINL –27V VS – 3.3V VA 8.7 LIN Pre-wake pull-up current V S < 27V V LIN = 0V 6ILINWAKE –30 –10 µA A 9 Internal Timers 9.1 Dominant time for wake-up via LIN bus V LIN = 0V 6 t BUS 30 90 150 µs A 9.2 Time of low pulse for wake-up via pin WAKE VWAKE = 0V 3 tWAKE 735 50 µs A 9.3 Time delay for mode change from fail-safe mode to normal mode via pin EN VEN = 5V 2 tnorm 2 7 15 µs A 9.4 Time delay for mode change from normal mode into sleep mode via pin EN V EN = 0V 2 t sleep 715 24 µs A 9.5 Atmel ATA6663: TXD dominant time out time V TXD = 0V 4 t dom 40 60 85 ms A 9.6 Power-up delay between VS =5V until INH switches to high VVS = 5V 7, 8 tVS 200 µs A 9.7 Monitoring time for wake-up via LIN bus 6tmon 610 15 ms A 6. Electrical Characteristics (Continued) 5V < VS < 27V, Tj = –40°C to +150°C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter |
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