R5F2M110ANDD datasheet(7/48 Pages) RENESAS

7 / 48 page

R8C/M11A Group, R8C/M12A Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0010EJ0010 Rev.0.10

Page 7 of 45

Aug 25, 2010

1.3

Block Diagram

Figure 1.2 shows the Block Diagram.

Figure 1.2

Block Diagram

I/O ports

Watchdog timer

(14 bits)

System clock generation

circuit

XIN-XOUT

High-speed on-chip oscillator

Low-speed on-chip oscillator

Timers

Timer RJ2 (16 bits

× 1)

Timer RB2 (8 bits

× 1

or 16 bits

× 1)

Timer RC (16 bits

× 1)

A/D converter

(10 bits

× 6 channels)

UART

Clock synchronous serial I/O

Clock asynchronous serial I/O

Peripheral functions

Voltage detection circuit

RAM (2)

Multiplier

USP

INTB

ISP

FLG

R8C CPU core

Memory

ROM (1)

R0H

R1H

R0L

R1L

Notes:

1. ROM size varies with the product.

2. RAM size varies with the product.

Port P1

Port P3

Port P4

Port PA

Comparator B

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