6402 datasheet(30/250 Pages) INTEL

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DDR Interface

Intel® 6400/6402 Advanced Memory Buffer Datasheet

initialization, DDR I/O calibration, and normal operation where the FBD channel issues

DRAM commands. The DAREFTC CSR controls the refresh interval and period, and

includes an enable bit to turn auto-refresh command generation on and off. The auto-

refresh FSM may be integrated or separate from the MemBIST functions in hardware,

but the auto-refresh function runs independently of the MemBIST state. Multiple

MemBIST tests can be started and completed with the auto-refresh FSM running

during, in between, and after all MemBIST tests complete.

The Auto-Refresh FSM generates auto-refresh command requests to an arbiter in

hardware at regularly spaced intervals defined by the DAREFTC.TREFI CSR. For a single

rank DIMM the command spacing is equal to TREFI cycles. For dual rank DIMMs the

command spacing is TREFI/2, alternating between the two ranks so that each rank

receives an auto-refresh command every TREFI cycles on average. Hardware abitrates

between the Self-Refresh FSM command requests and commands generated by the

MemBIST function. When MemBIST is not running, the auto-refresh command is

immediately issued on the DDR bus. When MemBIST is running, an auto-refresh

request is posted until the MemBIST FSM can interrupt its command sequence,

precharge all open banks on all ranks, and all DRAM timing requirements are met so

that an auto-refresh command can be accepted. The MemBIST FSM resumes its

command sequence TRFC later. The MemBIST FSM must interrupt its operation within

TREFI/2 in order to avoid causing an auto-refresh command to be dropped by the

arbiter.

3.6

Back to Back Turnaround Time

The host controller is required to observe a turnaround time on the DRAM data pins

within a DIMM when switching between read and write cycles, and when switching from

reads from one rank vs. the other rank on the DIMM. The nominal turnaround time is

one clock for each parameter, which is the minimum time required to prevent a collision

of the postamble of the first transaction and preamble of the second transaction.

Additional clocks may be required by the DIMM, especially at higher speeds.

The three timing parameters are:

• Read to write turnaround time. The number of additional DRAM clocks in which the

DRAM data bus must be idle between a read from either rank and a write cycle to

either rank.

• Write to read turnaround time. The number of additional DRAM clocks in which the

DRAM data bus must be idle between a write to one rank and a read from either

rank. The write to read turnaround time to the same rank will generally dominated

by the tWTR specification, which must also be observed.

• Read to read turnaround time. The number of additional DRAM clocks in which the

DRAM data bus must be idle between a read from one rank and a read from the

opposite rank.

These parameters are dependent on the AMB design and the DIMM PC board layout.

The parameters are stored in the SPD. Each parameter is a 2 bit field allowing 0 to 3

additional clocks of turnaround time. See the FB4300/5300/6400 DDR2 Fully Buffered

DIMM Design Specification for additional details.

Figure 3-1 shows the nominal turnaround times, with no additional clocks. Note that

the DQS preamble and postamble may merge slightly when the first transaction is at

worst case timings and the second transaction is at best case timings.

6402 Datasheet(PDF) 30 Page - Intel Corporation

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