910GL datasheet(90/426 Pages) INTEL

90 / 426 page

Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

4.1.27

SMRAM—System Management RAM Control (D0:F0)

PCI Device:

Address Offset:

9Dh

Default Value:

00h

Access:

R/W/L, RO

Size:

8 bits

The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are

treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also,

the OPEN bit must be reset before the LOCK bit is set.

Bit

Access &

Default

Description

Reserved

R/W/L

SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM

space DRAM is made visible even when SMM decode is not active. This is

intended to help BIOS initialize SMM space. Software should ensure that

D_OPEN=1 and D_CLS=1 are not set at the same time.

R/W/L

SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not

accessible to data references, even if SMM decode is active. Code references

may still access SMM space DRAM. This will allow SMM software to reference

through SMM space to update the display even when SMM is mapped over the

VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set

at the same time. Note that the D_CLS bit only applies to Compatible SMM

space.

R/W/L

SMM Space Locked (D_LCK): When D_LCK is set to 1, D_OPEN is reset to 0

and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and

TSEG_EN become read only. D_LCK can be set to 1 via a normal configuration

space write but can only be cleared by a full Reset. The combination of D_LCK

and D_OPEN provide convenience with security. The BIOS can use the

D_OPEN function to initialize SMM space and then use D_LCK to "lock down"

SMM space in the future so that no application software (or BIOS itself) can

violate the integrity of SMM space, even if the program has knowledge of the

D_OPEN function.

R/W/L

Global SMRAM Enable (G_SMRAME): If set to a 1, Compatible SMRAM

functions are enabled, providing 128 KB of DRAM accessible at the A0000h

address while in SMM (ADSB with SMM decode). To enable Extended SMRAM

function this bit has be set to 1. Refer to the section on SMM for more details.

Once D_LCK is set, this bit becomes read only.

2:0

010b

Compatible SMM Space Base Segment (C_BASE_SEG): This field indicates

the location of SMM space. SMM DRAM is not remapped. It is simply made

visible if the conditions are right to access SMM space, otherwise the access is

forwarded to DMI. Since the (G)MCH supports only the SMM space between

A0000h and BFFFFh, this field is hardwired to 010.

910GL Datasheet(PDF) 90 Page - Intel Corporation

910GL Datasheet(HTML) 90 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL