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910GL Datasheet(PDF) 103 Page - Intel Corporation

Part # 910GL
Description  Express Chipset
PDF  426 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

910GL Datasheet(HTML) 103 Page - Intel Corporation

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MCHBAR Registers
R
Datasheet
103
Bit
Access &
Default
Description
6:4
R/W
010b
DRAM RAS to CAS Delay (tRCD). This bit controls the number of clocks inserted
between a row activate command and a read or write command to that row.
000 = 2 DRAM clocks
001 = 3 DRAM clocks
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
3
Reserved
2:0
R/W
010b
DRAM RAS Precharge (tRP). This bit controls the number of clocks that are
inserted between a row precharge command and an activate command to the
same rank.
000 = 2 DRAM clocks
001 = 3 DRAM clocks
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved



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