910GL datasheet(109/426 Pages) INTEL

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EPBAR Registers—Egress Port Register Summary

Datasheet

109

EPBAR Registers—Egress Port

These registers are offset from the EPBAR base address.

Table 6-1. Egress Port Register Address Map

Address

Offset

Symbol

Default

Value

Access

044h–047h

EPESD

EP Element Self Description

0000h

R/WO, RO

050h–053h

EPLE1D

EP Link Entry 1 Description

0100h

R/WO, RO

058h–

05Fh

EPLE1A

EP Link Entry 1 Address

000000000

0000000h

R/WO, RO

060h–063h

EPLE2D

EP Link Entry 2 Description

02000002h

R/WO, RO

068h–

06Fh

EPLE2A

EP Link Entry 2 Address

000000000

0008000h

6.1

EP RCRB Configuration Register Details

Figure 6-1. Link Declaration Topology

PEG

(Port #2)

Egress_LinkDeclar_Topo

Egress Port

(Port #0)

DMI

(Port #1)

Link #2

(Type 1)

Link #1

(Type 0)

Link #2

(Type 0)

Link #1

(Type 0)

Egress Port

(Port #0)

X16

(G)MCH

Main Memory

Subsystem

Intel® ICH6

Link #1

(Type 0)

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