PSD813F1A datasheet(38/111 Pages) STMICROELECTRONICS

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PSD813F1A

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Output Macrocell (OMC)

Eight of the Output Macrocells (OMC) are con-

nected to Ports A and B pins and are named as

McellAB0-McellAB7. The other eight macrocells

are connected to Ports B and C pins and are

named as McellBC0-McellBC7. If an McellAB out-

put is not assigned to a specific pin in PSDabel,

the Macrocell Allocator will assign it to either Port

A or B. The same is true for a McellBC output on

Port B or C. Table 14 shows the macrocells and

Port assignment.

The Output Macrocell (OMC) architecture is

shown in Figure 18., page 40. As shown in the fig-

ure, there are native product terms available from

the AND array, and borrowed product terms avail-

able (if unused) from other OMCs. The polarity of

the product term is controlled by the XOR gate.

The OMC can implement either sequential logic,

using the flip-flop element, or combinatorial logic.

The multiplexer selects between the sequential or

combinatorial logic outputs. The multiplexer output

can drive a Port pin and has a feedback path to the

AND array inputs.

The flip-flop in the OMC can be configured as a D,

T, JK, or SR type in the PSDabel program. The

flip-flop’s clock, preset, and clear inputs may be

driven from a product term of the AND array. Alter-

natively, the external CLKIN signal can be used for

the clock input to the flip-flop. The flip-flop is

clocked on the rising edge of the clock input. The

preset and clear are active-high inputs. Each clear

input can use up to two product terms.

Table 14. Output Macrocell Port and Data Bit Assignments

Output

Macrocell

Port

Assignment

Native Product Terms

Maximum Borrowed

Product Terms

Data Bit for Loading or

Reading

McellAB0

Port A0, B0

McellAB1

Port A1, B1

McellAB2

Port A2, B2

McellAB3

Port A3, B3

McellAB4

Port A4, B4

McellAB5

Port A5, B5

McellAB6

Port A6, B6

McellAB7

Port A7, B7

McellBC0

Port B0, C0

McellBC1

Port B1, C1

McellBC2

Port B2, C2

McellBC3

Port B3, C3

McellBC4

Port B4, C4

McellBC5

Port B5, C5

McellBC6

Port B6, C6

McellBC7

Port B7, C7

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