IXP45X datasheet(69/148 Pages) INTEL

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August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

Table 17.

UART Interfaces

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

RXDATA0

UART serial data input to UART Pins.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

TXDATA0

UART serial data output. The TXD signal is set to the MARKING (logic 1) state upon a reset

operation.

CTS0_N

VI/H

UART CLEAR-TO-SEND input to UART Pins.

When logic 0, this pin indicates that the modem or data set connected to the UART interface of the

processor is ready to exchange data. The signal is a modem status input whose condition can be

tested by the processor.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

RTS0_N

UART REQUEST-TO-SEND output:

When logic 0, this informs the modem or the data set connected to the UART interface of the

processor that the UART is ready to exchange data. A reset sets the request to send signal to logic 1.

LOOP-mode operation holds this signal in its inactive state (logic 1)

RXDATA1

UART serial data input.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

TXDATA1

UART serial data output. The TXD signal is set to the MARKING (logic 1) state upon a Reset

operation.

CTS1_N

VI/H

UART CLEAR-TO-SEND input to UART pins.

When logic 0, this pin indicates that the modem or data set connected to the UART interface of the

processor is ready to exchange data. The signal is a modem status input whose condition can be

tested by the processor.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

RTS1_N

UART REQUEST-TO-SEND output:

When logic 0, this informs the modem or the data set connected to the UART interface of the

processor that the UART is ready to exchange data. A reset sets the request to send signal to logic 1.

LOOP-mode operation holds this signal in its inactive state (logic 1).

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

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