C5NPD0-DS datasheet(21/100 Pages) FREESCALE

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Block Diagram

V 04

Block Diagram

The C-5TM network processor, has an architecture specifically designed for networking

applications. Figure 1 shows a block diagram of the C-5 NP, including its potential external

interfaces. The following sections describe each component of the C-5 NP.

For more information about the architecture of the C-5 NP, see the C-5 Network Processor

Architecture Guide.

Figure 1 C-5 Network Processor Block Diagram

The main components of the C-5 NP are:

• Channel Processors

• Executive Processor

• Fabric Processor

• Buffer Management Unit

• Table Lookup Unit

• Queue Management Unit

PHY

Buses (60Gbps Bandwidth)

Cluster

CP-1

CP-0

CP-2

CP-3

CP-12 CP-13 CP-14 CP-15

External

Host CPU

(optional)

OC-3

PHY Interface Examples:

OC-12

Gigabit Ethernet

10/100 Ethernet

External

PROM

(optional)

Control

Logic

(optional)

Fabric

Processor Boundary

Buffer

Mgmt

Unit

Channel

Processors

SDRAM

C-5

SRAM

Table

Lookup

Unit

Fabric

Processor

Executive Processor

Queue

Mgmt

Unit

PCI

Serial

PROM

Freescale Semiconductor, Inc.

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