©2009 CADEKA Microcircuits LLC

www.cadeka.com

2

Data Sheet

Pin Assignments

Pin No.

Pin Name

Description

0

VSS

Ground connection for all power domains. Exposed pad

1, 11, 16

DVDD

Digital and I/O-ring pre driver supply voltage, 1.8V

2

CM_EXT

Common Mode voltage output

3, 4, 7

AVDD

Analog supply voltage, 1.8V

5, 6

IP, IN

Analog input (non-inverting, inverting)

8

DVDDCLK

Clock circuitry supply voltage, 1.8V

9

CLKP

Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave)

10

CLKN

Clock input, inverting. For CMOS input on CLKP, Connect CLKN to ground

12

CLK_EXT_EN

CLK_EXT signal enabled when low (zero). Tristate when high.

13

DFRMT

Data format selection. 0: Offset Binary, 1: Two's Complement

14

PD_N

Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up

always apply Power Down mode before using Active Mode to reset chip.

15

OE_N

Output Enable. Tristate when high

17, 18, 25,

26, 36, 37

OVDD

I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V

19

D_0

20

D_1

21

D_2

Output Data

22

D_3

Output Data

Pin Configuration

QFN-40

CDK1307

QFN-40

2

CM_EXT

4

AVDD

3

AVDD

1

DVDD

6

IN

8

DVDDCLK

7

AVDD

10

CLKN

9

CLKP

5

IP

29 D_6

27 CLK_EXT

28 D_5

30 D_7

25 OVDD

23 D_4

24 ORNG

21 D_2

22 D_3

26 OVDD