MM912F634CV2AP datasheet(73/335 Pages) FREESCALE

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Functional Description and Application Information

Wake-up / Cyclic Sense

MM912F634

Freescale Semiconductor

4.8.1.2

Lx - Cyclic Sense Wake-up

NOTE

Once Cyclic Sense is configured (CSSEL!=0), the state change is only recognized from one

cyclic sense event to the next.

The additional accuracy of the cyclic sense cycle by the WD clock trimming is only active

during STOP mode. There is no trimmed clock available during SLEEP mode.

To reduce external power consumption during low power mode a cyclic wake-up has been implemented. Configuring the Timing

Control Register (TCR) a specific cycle time can be selected to implement a periodic switching of the HS1 or HS2 output with the

corresponding detection of an Lx state change. Any configuration of the HSx in the High Side Control Register (HSCR) will be

ignored when entering low power mode. The Lx - Cyclic Sense Wake-up may be combined with the Forced Wake-up. In case

both (forced and Lx change) events are present at the same time, the Forced Wake-up will be indicated as Wake-up source.

4.8.1.3

Forced Wake-up

Configuring the Forced Wake-up Multiplier (FWM) in the Timing Control Register (TCR) will enable the forced wake-up based on

the selected Cyclic Sense Timing (CST). Forced Wake-up can be combined with all other wake-up sources considering the timing

dependencies.

4.8.1.4

LIN - Wake-up

While in Low-Power mode the MM912F634 analog die monitors the activity on the LIN bus. A dominant pulse longer than

tPROPWL followed by a dominant to recessive transition will cause a LIN Wake-up. This behavior protects the system from a

short-to-ground bus condition.

4.8.1.5

D2D - Wake-up (Stop Mode only)

Receiving a Normal mode request via the D2D interface (MODE=0, Mode Control Register (MCR)) will result in a wake-up from

stop mode. As this condition is controlled by the MCU, no wake-up status bit does indicate this wake-up source.

4.8.1.6

Wake-up Due to Internal / External Reset (STOP Mode Only)

While in Stop mode, a Reset due to a VDD low voltage condition or an external Reset applied on the RESET_A pin will result in

a Wake-up with immediate transition to Reset mode. In this case, the LVR or EXR bits in the Reset Status Register will indicate

the source of the event.

4.8.1.7

Wake-up Due to Loss of Supply Voltage (SLEEP Mode Only)

While in Sleep mode, a supply voltage VS1 < VPOR will result in a transition to Power On mode.

MM912F634CV2AP Datasheet(PDF) 73 Page - Freescale Semiconductor, Inc