AT89LP51 datasheet(11/113 Pages) ATMEL

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3709B–MICRO–12/10

AT89LP51/52 - Preliminary

3.1.1

External Program Memory Interface

The AT89LP51/52 uses the standard 8051 external program memory interface with the upper

address on Port 2, the lower address and data in/out multiplexed on Port 0, and the ALE and

PSEN strobes. Program memory addresses are always 16-bits wide, even though the actual

amount of program memory used may be less than 64K byes. External program execution sacri-

fices two full 8-bit ports, P0 and P2, to the function of addressing the program memory.

Figure 3-2 shows a hardware configuration for accessing up to 64K bytes of external ROM using

a 16-bit linear address. Port 0 serves as a multiplexed address/data bus to the ROM. The

Address Latch Enable strobe (ALE) is used to latch the lower address byte into an external reg-

ister so that Port 0 can be freed for data input/output. Port 2 provides the upper address byte

throughout the operation. PSEN strobes the external memory.

Figure 3-3 shows the timing of the external program memory interface. ALE is emitted at a con-

stant rate of 1/3 of the system clock with a 1/3 duty cycle. PSEN is emitted at a similar rate, but

with 50% duty cycle. The new address changes in the middle of the ALE pulse for latching on

the falling edge and is tristated at the falling edge of PSEN. The instruction data is sampled from

P0 and latched internally during the high phase of the clock prior to the rising edge of PSEN.

This timing applies to both Compatibility and Fast modes. In Compatibility mode there is no dif-

ference in instruction timing between internal and external execution.

Figure 3-2.

Executing from External Program Memory

Figure 3-3.

External Program Memory Fetches

AT89LP

EXTERNAL

PROGRAM

MEMORY

INSTR.

ADDR

PSEN

ALE

LATCH

CLK

ALE

PSEN

FLOAT

PCL

OUT

PCH OUT

DATA

SAMPLED

PCL

OUT

PCL

OUT

DATA

SAMPLED

DATA

SAMPLED

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