FMP3216DAx

CMOS LPRAM

2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM

FEATURES

• Organization : 2M x 16

• Power Supply Voltage 2.7V ~ 3.3V

• Three state output and TTL Compatible

• Separated I/O power(VCCQ) & Core power(VCC)

• Operating Temperature Ranges:

Special (-10’C to +60’C)

Commercial (0’C to +70’C)

Et d d ( 25’C t

85’C)

FMP3216DAx-HxxX : Pb-Free & Halogen Free

• Low Power & Page Modes

FMP3216DA1 : support the PASR/DPD function

FMP3216DA2 : support the Direct DPD function

FMP3216DA4 : support the PASR/DPD/PAGE function

FMP3216DA5 : support the Direct DPD/PAGE function

• Page read operation by 16 words

(FMP3216DA4, FMP3216DA5)

• DPD mode by using MRS only

PRODUCT FAMILY

Product Family

Operating

Voltage (V)

Speed

Power Dissipation

ICC1

ICC2

ISB1

(CMOS Standby

Current)

Min. Typ. Max.

f = 1MHz

f = fmax

Extended (-25’C to +85’C)

Industrial (-40’C to +85’C)

DPD mode by using MRS only

(FMP3216DA1, FMP3216DA4)

• Direct DPD mode when /ZZ goes low

(FMP3216DA2, FMP3216DA5)

PIN DESCRIPTION

1

2

3

4

5

6

FUNCTIONAL BLOCK DIAGRAM

Min. Typ. Max.

Typ.

Max.

Typ.

Max.

Typ.

Max.

FMP3216DAx-H70E

2.7

3.0

3.3

60ns

70ns

1.5mA

3mA

15mA

12mA

20mA

90uA

120uA

2. H=FBGA(Pb-Free & Halogen Free), W=WAFER

3. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C)

A

B

C

D

/LB

/OE

A0

A1

A2

I/O9

/UB

A3

A4

/CS

I/O10

I/O11

A5

A6

I/O2

VSS

I/O12

A17

A7

I/O4

/ZZ

I/O1

I/O3

VCC

Precharge circuit.

Clk gen.

VCC

VSS

Memory array

Row

Addresses

Row

select

E

F

G

H

VCCQ

I/O13

DNU

A16

I/O5

I/O15

I/O14

A14

A15

I/O6

I/O16

A19

A12

A13

WE

A18

A8

A9

A10

A11

VSS

I/O7

I/O8

A20

48 FBGA : Top View(Ball Down)

I/O Circuit

Column select

Data

cont

Data

cont

Data

cont

I/O9~I/O16

I/O1~I/O8

48-FBGA : Top View(Ball Down)

Name

Function

Name

Function

/ZZ

Low Power Modes

VCC

Core Power

/CS

Chip Select Input

VCCQ

I/O Power

/OE

Output Enable Input

VSS

Ground

/WE

Write Enable Input

/UB

Upper Byte(I/O9~16)

A0 A20

Add

I

t

/LB

L

B t (I/O 1 8)

Column Addresses

Control Logic

/CS

/OE

/WE

/UB

/LB

Revision 0.1

Jul. 2010

2

A0~A20

Address Inputs

/LB

Lower Byte(I/O 1~8)

I/O1~I/O16

Data Inputs/Outputs

DNU

Do Not Use

/LB

/ZZ