PCF8563_11 datasheet(29/45 Pages) NXP

29 / 45 page

PCF8563

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Product data sheet

Rev. 9 — 16 June 2011

29 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

[1]

For reliable oscillator start-up at power-up: VDD(min)power-up =VDD(min) +0.3 V.

[2]

Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.

[3]

Tested on sample basis.

Outputs

IOL

LOW-level

output current

output sink current;

VOL =0.4 V; VDD =5V

on pin SDA

on pin INT

on pin CLKOUT

ILO

output leakage

current

VO =VDD or VSS

10

A

Voltage detector

Vlow

low voltage

Tamb =25 C; sets bit VL; see Figure 7

-0.9

1.0

Table 29.

Static characteristics …continued

VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs =40 k; CL = 8 pF; unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Tamb =25 C; Timer = 1 minute.

Fig 24. Supply current IDD as a function of supply

voltage VDD; CLKOUT disabled

Fig 25. Supply current IDD as a function of supply

voltage VDD; CLKOUT = 32 kHz

mgr888

VDD (V)

0.4

0.2

0.8

0.6

IDD

(

μA)

mgr889

VDD (V)

0.4

0.2

0.8

0.6

IDD

(

μA)

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