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ZL2103ALAF Datasheet(PDF) 2 Page - Intersil Corporation

Part # ZL2103ALAF
Description  3A Digital-DC Synchronous Step-Down DC/DC Converter
PDF  28 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ZL2103ALAF Datasheet(HTML) 2 Page - Intersil Corporation

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ZL2103
2
FN6966.5
May 3, 2011
Typical Application Circuit
The following application circuit represents a typical
implementation of the ZL2103. For PMBus operation, it is
recommended to tie the enable pin (EN) to SGND.
Block Diagram
VOUT
3.3V
VIN
12V
I2C/
SMBus††
DDC Bus†
ENABLE
CB
47nF
C25
10µF
CDD
2.2µF
COUT
150µF
LOUT
2.2µH
CIN
100µF
VSET
SA
SCL
SDA
SALRT
FC
PG
SYNC
DGND
ZL2103
SW
SW
SW
SW
SW
PGND
VDDP
SW
BST
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
PGOOD
CRA
4.7µF
CR
4.7µF
F.B.
‡
Notes:
‡ Ferrite bead is optional for input noise suppression.
† The DDC bus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices
connected. The 10 k
♦ default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise
time. Please refer to the Digital-DC Bus section for more details.
†† The I2C/SMBus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices
connected. Please refer to the I2C/SMBus specifications for more details.
FIGURE 2. 12V TO 3.3V/3A APPLICATION CIRCUIT (5ms SS DELAY, 5ms SS RAMP)
Ω
2.5V
LDO
PWM
Control
&
Drivers
BST
VSEN
VSET
VTRK
SS
PG
EN
CFG
SW
7V
LDO
SMBus
SA
NVM
Power
Mgmt
DDC Bus
DDC
VOUT
MGN
VIN
5V
LDO
FIGURE 3. BLOCK DIAGRAM



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