LIS3DH datasheet(12/42 Pages) STMICROELECTRONICS

12 / 42 page

Mechanical and electrical specifications

LIS3DH

12/42

Doc ID 17530 Rev 1

2.4

Communication interface characteristics

2.4.1

SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Figure 3.

SPI slave timing diagram

Note:

Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on

characterization results, not tested in production.

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port.

When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal

pull-up resistors.

Table 6.

SPI slave timing values

Symbol

Parameter

Value (1)

Unit

Min

Max

tc(SPC)

SPI clock cycle

100

fc(SPC)

SPI clock frequency

MHz

tsu(CS)

CS setup time

th(CS)

CS hold time

tsu(SI)

SDI input setup time

th(SI)

SDI input hold time

tv(SO)

SDO valid output time

th(SO)

SDO output hold time

tdis(SO)

SDO output disable time

SPC

SDI

SDO

tsu(CS)

tv(SO)

th(SO)

th(SI)

tsu(SI)

th(CS)

tdis(SO)

tc(SPC)

MSB IN

MSB OUT

LSB OUT

LSB IN

(3)

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