5

5 - 140

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Truth Table

TTL/CMOS Control Voltages

State

Bias Condition

Low

0 to 0.8 Vdc @ -5 uA Typ.

High

+2.0 to +5.0 Vdc @ 40 uA Typ.

Control Voltage Input

Attenuation Setting

RF1 - RF2

V1

4 dB

V2

2 dB

V3

1 dB

High

High

High

Reference I.L.

High

High

Low

1 dB

High

Low

High

2 dB

Low

High

High

4 dB

Low

Low

Low

7 dB

Any combination of the above states will provide an attenuation

approximately equal to the sum of the bits selected.

Worst Case Step Error

Between Successive Attenuation States

-1

-0.6

-0.2

0.2

0.6

1

012345

6

FREQUENCY (GHz)

Bias Voltage & Current

Vdd Range= +5.0 Vdc ± 10%

Vdd

(Vdc)

Idd (Typ.)

(mA)

Idd (Max.)

(mA)

+5.0

1.05

1.8

HMC468LP3 / 468LP3E

v03.1107

1 dB LSB GaAs MMIC 3-BIT DIGITAL

POSITIVE CONTROL ATTENUATOR, DC - 6 GHz