FM22LD16 - 256Kx16 FRAM

Rev. 2.0

Dec. 2009

Page 2 of 14

Figure 1. Block Diagram

Pin Description

Pin Name

Type

Pin Description

A(17:0)

Input

Address inputs: The 18 address lines select one of 262,144 words in the F-RAM array. The

lowest two address lines A(1:0) may be used for page mode read and write operations.

/CE

Input

Chip Enable input: The device is selected and a new memory access begins when /CE is

low. The entire address is latched internally on the falling edge of /CE. Subsequent changes

to the A(1:0) address inputs allow page mode operation when /CE is low.

/WE

Input

Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the

FM22LD16 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE

latches a new column address for page mode write cycles.

/OE

Input

Output Enable: When /OE is low, the FM22LD16 drives the data bus when valid read data is

available. Deasserting /OE high tri-states the DQ pins.

DQ(15:0)

I/O

Data: 16-bit bi-directional data bus for accessing the F-RAM array.

/UB

Input

Upper Byte Select: Enables DQ(15:8) pins during reads and writes. Deasserting /UB high

tri-states the DQ pins. If the user does not perform byte writes and the device is not

configured as a 512Kx8, the /UB and /LB pins may be tied to ground.

/LB

Input

Lower Byte Select: Enables DQ(7:0) pins during reads and writes. Deasserting /LB high tri-

states the DQ pins. If the user does not perform byte writes and the device is not configured

as a 512Kx8, the /UB and /LB pins may be tied to ground.

VDD

Supply

Supply Voltage

VSS

Supply

Ground