HT48R063B datasheet(39/84 Pages) HOLTEK

39 / 84 page

HT48R063B/064B/065B/066B

Rev. 1.00

April 7, 2011

· TMR0C Register

Bit

76543210

Name

T0M1

T0M0

T0S

T0ON

T0EG

T0PSC2

T0PSC1

T0PSC0

R/W

POR

00001000

Bit 7,6

T0M1, T0M0: Timer0 operation mode selection

00: no mode available

01: event counter mode

10: timer mode

11: pulse width capture mode

Bit 5

T0S: timer clock source

0: fSYS

1: LXT oscillator

T0S selects the clock source for fTP which is provided for Timer 0, Timer 2, the Time-Base and

the PWM. If the PWM is enabled, then fSYS will be selected, overriding the T0S selection.

Bit 4

T0ON: Timer/event counter counting enable

0: disable

1: enable

Bit 3

T0EG:

Event counter active edge selection

0: count on raising edge

1: count on falling edge

Pulse Width Capture active edge selection

0: start counting on falling edge, stop on rasing edge

1: start counting on raising edge, stop on falling edge

Bit 2~0

T0PSC2, T0PSC1, T0PSC0: Timer prescaler rate selection

Timer internal clock=

000: fTP

001: fTP/2

010: fTP/4

011: fTP/8

100: fTP/16

101: fTP/32

110: fTP/64

111: fTP/128

· TMR1C Register

Bit

76543210

Name

T1M1

T1M0

T1S

T1ON

T1EG

¾¾¾

R/W

¾¾¾

POR

00001

¾¾¾

Bit 7,6

T1M1, T1M0: Timer1 operation mode selection

00: no mode available

01: event counter mode

10: timer mode

11: pulse width capture mode

Bit 5

T1S: timer clock source

0: fSYS/4

1: LXT oscillator

Bit 4

T1ON: Timer/event counter counting enable

0: disable

1: enable

Bit 3

T1EG:

Event counter active edge selection

0: count on raising edge

1: count on falling edge

Pulse width capture active edge selection

0: start counting on falling edge, stop on rasing edge

1: start counting on raising edge, stop on falling edge

Bit 2~0

unimplemented, read as

²0²

HT48R063B Datasheet(PDF) 39 Page - Holtek Semiconductor Inc

HT48R063B Datasheet(HTML) 39 Page - Holtek Semiconductor Inc

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