ICS9UMS9610 datasheet(11/20 Pages) IDT

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IDTTM/ICSTM PC MAIN CLOCK

1336—06/01/09

ICS9UMS9610

PC MAIN CLOCK

Byte

Output Enable Register

Bit(s)

Pin #

Name

Description

Type

Default

CPU0 Enable

This bit controls whether the CPU[0] output

buffer is enabled or not.

0 = Disabled

1 = Enabled

CPU1 Enable

This bit controls whether the CPU[1] output

buffer is enabled or not.

0 = Disabled

1 = Enabled

CPU2 Enable

This bit controls whether the CPU[2] output

buffer is enabled or not.

0 = Disabled

1 = Enabled

SRC0 Enable

This bit controls whether the SRC[0] output

buffer is enabled or not.

0 = Disabled

1 = Enabled

SRC1 Enable

This bit controls whether the SRC[1] output

buffer is enabled or not.

0 = Disabled

1 = Enabled

SRC2 Enable

This bit controls whether the SRC[2] output

buffer is enabled or not.

0 = Disabled

1 = Enabled

DOT Enable

This bit controls whether the DOT output

buffer is enabled or not.

0 = Disabled

1 = Enabled

LCD100 Enable

This bit controls whether the LCD output buffer

is enabled or not.

0 = Disabled

1 = Enabled

Byte

Output Control Register

Bit(s)

Pin #

Name

Description

Type

Default

Reserved

REF Enable

This bit controls whether the REF output

buffer is enabled or not.

0 = Disabled

1 = Enabled

CPU0 Stop

Enable

This bit controls whether the CPU[0] output

buffer is free-running or stoppable. If it is set

to stoppable the CPU[0] output buffer will be

disabled with the assertion of CPU_STP#.

Free Running

Stoppable

CPU1 Stop

Enable

This bit controls whether the CPU[1] output

buffer is free-running or stoppable. If it is set

to stoppable the CPU[1] output buffer will be

disabled with the assertion of CPU_STP#.

Free Running

Stoppable

CPU2 Stop

Enable

This bit controls whether the CPU[2] output

buffer is free-running or stoppable. If it is set

to stoppable the CPU[2] output buffer will be

disabled with the assertion of CPU_STP#.

Free Running

Stoppable

00 = Slow Edge Rate

01 = Medium Edge Rate

10 = Fast Edge Rate

11 = Reserved

These bits control the edge rate of the REF

clock.

REF Slew

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