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ADL5812ACPZ-R7 Datasheet(PDF) 4 Page - Analog Devices

Part # ADL5812ACPZ-R7
Description  Dual High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADL5812ACPZ-R7 Datasheet(HTML) 4 Page - Analog Devices

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ADL5812
Rev. 0 | Page 4 of 28
TIMING CHARACTERISTICS
Low logic level ≤ 0.4 V, and high logic level ≥ 1.4 V.
Table 2. Serial Interface Timing
Parameter
Limit
Unit
Test Conditions/Comments
t1
20
ns minimum
LE setup time
t2
10
ns minimum
DATA-to-CLK setup time
t3
10
ns minimum
DATA-to-CLK hold time
t4
25
ns minimum
CLK high duration
t5
25
ns minimum
CLK low duration
t6
10
ns minimum
CLK-to-LE setup time
t7
20
ns minimum
LE pulse width
Timing Diagram
CLK
DATA
LE
DB23 (MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
(CONTROL BIT C3)
DB0 (LSB)
(CONTROL BIT C1)
t2
t3
t7
t6
t1
t4
t5
Figure 2. Timing Diagram



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