Data Sheet

ADDI9023

Rev. 0 | Page 11 of 12

CIRCUIT LAYOUT INFORMATION

The recommended circuit configuration is shown in Figure 8.

Each supply pin should have a high quality 0.1 µF capacitor

connected to ground. The VH and VL supplies should have an

additional bypass capacitor, such as a 1.0 µF to 22 µF capacitor,

depending on CCD and performance requirements. Connect the

ground pins (VSS, VM, and VMM) to a common ground plane.

ADDI9023

(Not to Scale)

XV8

XV7

XSG1

XV1

XSG2

XSG3

XV2

XSG4

XV3

XSG6

XV4

XSG7

XV6

XSG8

XV9

XSUBCK

XSG5

XV5

18

C6

D6

C7

F4

B5

B6

F5

B7

F6

A7

F7

B4

E7

A5

D7

F3

A6

E6

V1A

V1B

V2A

V2B

V3A

V3B

V5

V6

V8

V7

SUBCK

V4

V9

13

G1

F1

F2

E1

E2

D2

C2

C1

B1

B2

G2

D1

B3

25V

10V

0.1µF

+3.3V SUPPLY

VH SUPPLY

VL SUPPLY

1.0µF

25V

4.7µF

0.1µF

0.1µF

10V

+

V-DRIVER OUTPUTS

(TO CCD)

LOGIC INPUTS

(FROM

TIMING GENERATOR)

A4

VDREN

V-DRIVER OUTPUT ENABLE

ACTIVE HIGH (FROM

GENERAL-PURPOSE OUTPUT)

Figure 8. Typical Circuit Configuration