ADP1047ARQZ-R7 datasheet(75/84 Pages) AD

75 / 84 page

Data Sheet

ADP1047/ADP1048

Rev. 0 | Page 75 of 84

VAC ADC GAIN TRIM REGISTER

This register must be unlocked for write access; see Table 61.

Table 125. Register 0xFE40—VAC ADC Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

VAC ADC gain trim

R/W

This value calibrates the VAC voltage sense gain.

VFB ADC GAIN TRIM REGISTER

This register must be unlocked for write access; see Table 61.

Table 126. Register 0xFE41—VFB ADC Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

VFB ADC gain trim

R/W

This value calibrates the output voltage sense gain.

CS ADC GAIN TRIM FOR 500 mV RANGE REGISTER

This register must be unlocked for write access; see Table 61.

Table 127. Register 0xFE42—CS ADC Gain Trim for 500 mV Range

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS ADC gain trim

R/W

This value calibrates the CS current sense gain.

IBAL GAIN REGISTER (ADP1048 ONLY)

Table 128. Register 0xFE43—IBAL Gain (ADP1048 Only)

Bits

Bit Name

R/W

Description

IBAL enable

R/W

1 = enable current balancing.

0 = disable current balancing and reset the IBAL integrator.

[6:0]

IBAL gain

R/W

The gain can be set from 0 to 127.

SMART VOUT LOW POWER THRESHOLD (P1) REGISTER

Table 129. Register 0xFE44—Smart VOUT Low Power Threshold (P1)

Bits

Bit Name

R/W

Description

[15:13]

RSVD

Reserved.

[12:0]

R/W

These bits set the threshold value for low power mode operation when the smart output

voltage function is enabled. When the input power is lower than this value, the output voltage

is VOL1 for low line input and VOH1 for high line input.

SMART VOUT HIGH POWER THRESHOLD (P2) REGISTER

Table 130. Register 0xFE45—Smart VOUT High Power Threshold (P2)

Bits

Bit Name

R/W

Description

[15:13]

RSVD

Reserved.

[12:0]

R/W

These bits set the threshold value for high power mode operation when the smart output

voltage function is enabled. When the input power is higher than this value, the output

voltage is VOL2 for low line input and VOH2 for high line input.

ADP1047ARQZ-R7 Datasheet(PDF) 75 Page - Analog Devices

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