ADP1048ARQZ-R7 datasheet(58/84 Pages) AD

58 / 84 page

ADP1047/ADP1048

Data Sheet

Rev. 0 | Page 58 of 84

CS_FAST_OCP_RESPONSE REGISTER

This register instructs the device on actions to take due to a fast overcurrent protection condition.

Table 62. Register 0xFE00—CS_FAST_OCP_RESPONSE

Bits

Bit Name

R/W

Description

[7:6]

Response

R/W

These bits determine the device response to a fast overcurrent protection condition.

Bit 7

Bit 6

Response

Ignore (still terminate the PWM pulse).

Allow the number of switching cycles specified in Bits[5:4], then shut down and

soft start (use the soft start delay time specified in Register 0x5C, Bits[2:0]).

Allow the number of switching cycles specified in Bits[5:4] (terminating the PWM

pulse each time), then shut down and wait for the PSON signal to soft start.

Disable the PWM output after the number of switching cycles specified in Bits[5:4]

and wait for the flag to be cleared.

[5:4]

N-time

R/W

These bits determine the number of switching cycles allowed before the device disables the PWM

output after a fast overcurrent condition is detected.

Bit 5

Bit 4

Number of Switching Cycles

[3:0]

RSVD

Reserved.

OVP_FAST_OVP_RESPONSE REGISTER

This register instructs the device on actions to take due to a fast overvoltage fault condition.

Table 63. Register 0xFE01—OVP_FAST_OVP_RESPONSE

Bits

Bit Name

R/W

Description

[7:6]

Response

R/W

These bits determine the device response to a fast overvoltage condition.

Bit 7

Bit 6

Response

Ignore (do nothing; PWM continues).

Shut down and soft start.

Shut down immediately and wait for the PSON signal.

Disable the PWM output until the unlatched flag is cleared.

[5:0]

RSVD

Reserved.

OLP_RESPONSE REGISTER

This register instructs the device on actions to take due to an open-loop fault condition.

Table 64. Register 0xFE02—OLP_RESPONSE

Bits

Bit Name

R/W

Description

[7:6]

Response

R/W

These bits determine the device response to an open-loop fault condition.

Bit 7

Bit 6

Response

Ignore (do nothing; PWM continues).

Shut down and soft start.

Shut down immediately and wait for the PSON signal.

Disable the PWM output until the unlatched flag is cleared.

[5:0]

RSVD

Reserved.

ADP1048ARQZ-R7 Datasheet(PDF) 58 Page - Analog Devices

ADP1048ARQZ-R7 Datasheet(HTML) 58 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL