ADP5040ACPZ-1-R7 datasheet(34/40 Pages) AD

34 / 40 page

ADP5040

Data Sheet

Rev. 0 | Page 34 of 40

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5040 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines:

•

Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.

•

Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

•

Maximize the size of ground metal on the component side

to help with thermal dissipation.

•

Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference

on sensitive circuit nodes.

SUGGESTED LAYOUT

See Figure 109 for an example layout.

AGND

VOUT3

VOUT1

VOUT2

P P L

G P L

P P L

TOP LAYER

VIAS LEGEND:

PPL = POWER PLANE (+4V)

GPL = GROUND PLANE

2ND LAYER

MODE

L1 – 1µH

0603

C5 – 4.7µF

10V/XR5 0603

C6 – 10µF

6.3V/XR5

0603

1.0

2.0

3.0

4.0

5.0

6.0

6.5

7.0

0.5

1.5

2.5

3.5

4.5

5.5

RFILT

Ω

0402

C3 – 1µF

10V/XR5

0402

C4– 2.2µF

6.3V/XR5

0402

C2 – 1µF

10V/XR5

0402

C5 – 2.2µF

6.3V/XR5

0402

AVIN

VIN

PGND

EN1

ADP5040

Figure 109. Evaluation Board Layout

ADP5040ACPZ-1-R7 Datasheet(PDF) 34 Page - Analog Devices

ADP5040ACPZ-1-R7 Datasheet(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL