SP504 datasheet(14/31 Pages) SIPEX

14 / 31 page

Rev: A Date:1/27/04

SP504 Multi–Mode Serial Transceivers

Figure 17. Charge Pump Waveforms

Figure 14a. Charge Pump Phase 2 for

±10V.

Figure 15. Charge Pump Phase 3.

VCC = +5V

–10V

VDD Storage Capacitor

–

VSS Storage Capacitor

–

VCC = +5V

–5V

+5V

VDD Storage Capacitor

–

VSS Storage Capacitor

–

Figure 16. Charge Pump Phase 4.

Figure 14b. Charge Pump Phase 2 for

±5V.

VCC = +5V

VDD Storage Capacitor

–

VSS Storage Capacitor

–

–5V

VCC = +5V

+10V

VDD Storage Capacitor

–

VSS Storage Capacitor

–

GND

–10V

+10V

–

(a)

(b)

GND

+5V

GND

–

–5V

Phase 2 (±10V)

— V

SS transfer — Phase two of the clock con-

nects the negative terminal of C

2 to the VSS

storage capacitor and the positive terminal of C

to ground, and transfers the generated –l0V or

the generated –5V to C

3. Simultaneously, the

positive side of capacitor C

1 is switched to +5V

and the negative side is connected to ground.

Phase 2 (±5V)

— V

SS & VDD charge storage — C1

+ is recon-

nected to V

CC to recharge the C1 capacitor. C2

is switched to ground and C

– is connected to C

The 5V charge from Phase 1 is now transferred

to the V

SS storage capacitor.

SS receives a

continuous charge from either C

1 or C2. With

the C1 capacitor charged to 5V, the cycle begins

again.

Phase 3

— V

DD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C

1 produces –5V in the negative

terminal of C

1, which is applied to the negative

side of capacitor C

2. Since C2

+ is at +5V, the

voltage potential across C

2 is l0V. For the 5V

output, C

+ is connected to ground so that the

potential on C

2 is only +5V.

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