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CXD3003 Datasheet(PDF) 91 Page - Sony Corporation |
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CXD3003 Datasheet(HTML) 91 Page - Sony Corporation |
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91 / 137 page  – 91 – CXD3003R §4-9. DAC Block Playback Speed • The DAC block playback speed is controlled by sending the DADS command to the DSP block. Mode 1 2 768fs 384fs 0 1 X'tal DADS §4-10. DAC Block Input Timing The DAC input timing chart is shown below. Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD3003R. This is to allow data to be sent to the DAC block via the audio DSP, etc. When the data is input to the DAC block without using the audio DSP, the data must be connected outside the LSI. In this case, LRCK, BCK and PCMD can be connected directly with LRCKI, BCKI and PCMDI, respectively. (See the Application Circuit.) Normal-Speed Playback L15 Invalid L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L0 LRCKI (44.1k) BCKI (2.12M) PCMDI |
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